Memory device

ABSTRACT

A memory device that can handle various transmission-source devices and transmission-destination devices without modifying the hardware configuration. The memory device is used to transmit and receive data, and includes a data buffer for storing data output from a data-transmission source and outputting the data to a data-transmission destination serving as the data output destination; a transmission-source address converter for performing arrangement processing on the data output from the data-transmission source when the data-transmission source is a device that passively outputs data; and a transmission-destination address converter for performing arrangement processing on the data to be input to the data-transmission destination when the data-transmission destination is a device to which data is passively input.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefits of priority fromthe prior Japanese Patent Application No. 2005-216621, filed on Jul. 27,2005, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to memory devices, and more particularly,to a memory device that performs transmission and reception of data.

2. Description of the Related Art

In current computer systems and other devices, various buffers are usedto perform data transmission and reception.

For example, a known device for transferring data inside a singlecentral processing unit (CPU) is a stack memory, which is used as anarea for temporarily saving data such as register data and the like dueto interrupts and function calls. In general, the stack memory isimplemented using a stack pointer on a standard one-dimensional memory.

A known device for transferring data between different CPUs is a sharedmemory having a software-based interface.

A known device for transferring data between a CPU and a memory is acache memory.

Cache memories are data buffers with a relatively high degree ofversatility since hardware control is performed, and there is no needfor software that takes the hardware configuration into account. Also,because data swapping is automatically performed by hardware in cachememories, there is an advantage in that, regarding software-based dataaccess, data swapping is seamless.

However, because cache memories are restricted to data transfer in unitsequal to the cache line size, they are inefficient at handling discretedata. In addition, because they were originally based on technologyemploying temporal and spatial locality of data access, they suffer fromthe problem that the cache capacity is wastefully used up when accessingdata that is not reusable (that is, a part of the cache memories ismeaninglessly occupied), and the performance is therefore reduced. Theyalso suffer from the problem that the cache capacity significantlyaffects the computational performance of the CPU.

There is a known storage device provided with a stream buffer, combinedwith a cache memory, that can perform buffering without wastefully usingup the capacity of the cache (that is, without occupying a part of thecache memory meaninglessly), even for data that is not reusable (forexample, see Japanese Unexamined Patent Publication No. 09-319657).

However, stack memories and shared memories must be provided withdedicated hardware and software frameworks and therefore suffer frompoor versatility. Moreover, the storage device described in JapaneseUnexamined Patent Publication No. 09-319657 can be used only fortransmitting and receiving data between a CPU and a memory, but it isdifficult to use it in other configurations.

To summarize the above, hardware constituting conventional datatransmitting-and-receiving devices must be appropriately modified tomatch the device(s) to be controlled (CPU and/or memory) for performingdata transmission and reception. In other words, there is presently nosuitable framework that can provide a unified infrastructure for anytype of data communication.

SUMMARY OF THE INVENTION

The present invention has been conceived in light of the problemsdescribed above, and it is an object thereof to provide a memory devicethat can handle various transmission-source devices andtransmission-destination devices without modifying the hardwareconfiguration.

In order to realize the object mentioned above, a memory device for usein transmitting and receiving data is provided. This memory deviceincludes a data buffer for storing data output from a data-transmissionsource and outputting the data to a data-transmission destinationserving as an output destination for the data; a transmission-sourceaddress converter for performing arrangement processing on the dataoutput from the data-transmission source when the data-transmissionsource is a device that passively outputs data; and atransmission-destination address converter for performing arrangementprocessing on the data to be input to the data-transmission destinationwhen the data-transmission destination is a device to which data ispassively input.

The above and other objects, features and advantages of the presentinvention will become apparent from the following description when takenin conjunction with the accompanying drawings, which illustratepreferred embodiments of the present invention by way of example.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram showing the basic outline of the present invention.

FIG. 2 is a block diagram showing a data transmitting-and-receivingsystem.

FIG. 3 is a block diagram showing the internal configuration of aninput-address converter.

FIG. 4 is a block diagram showing the internal configuration of anoutput-address converter.

FIG. 5 is a block diagram showing the internal configuration of a shiftregister.

FIG. 6 is a block diagram showing the configuration of a RAM and anaddress controller.

FIG. 7 is a table showing six configurations of the datatransmitting-and-receiving system.

FIG. 8 is an outlined diagram showing an example of the write and readoperations of the RAM in option B.

FIG. 9 is an outlined diagram showing an example of the write and readoperations of the RAM in option E.

FIG. 10 is a block diagram showing a data transmitting-and-receivingsystem of configuration 1.

FIG. 11 is an outlined diagram of a first transfer mode.

FIG. 12 is an outlined diagram of an example using a consecutive accessmode.

FIG. 13 is an outlined diagram of a second transfer mode.

FIG. 14 is an outlined diagram showing an example using a distanceaccess mode.

FIG. 15 is an outlined diagram of a third transfer mode.

FIG. 16 is an outlined diagram showing an example using a multi-distanceaccess mode.

FIG. 17 is a block diagram showing a data transmitting-and-receivingsystem of configuration 2.

FIG. 18 is a block diagram showing a data transmitting-and-receivingsystem of configuration 3.

FIG. 19 is a block diagram showing a data transmitting-and-receivingsystem of configuration 4.

FIG. 20 is a block diagram showing a data transmitting-and-receivingsystem of configuration 5.

FIG. 21 is a block diagram showing a data transmitting-and-receivingsystem of configuration 6.

DESCRIPTION OF THE PREFERRED EMBODIMENT

An embodiment of the present invention will be described below withreference to the drawings.

FIG. 1 shows the basic outline of the present invention.

A data transmitting-and-receiving system 10 includes a memory device 1,a data-transmission source 2, and a data-transmission destination 3.

The memory device 1 includes a data buffer 4, a transmission-sourceaddress converter 5, and a transmission-destination address converter 6.

The data buffer 4 stores data output from the data-transmission source 2and outputs data to the data-transmission destination 3, which is theoutput destination of the data.

When the data-transmission source 2 is a device that passively outputsdata, that is, when the data-transmission source 2 outputs data to thedata buffer 4 only if the data-transmission source 2 receives anexternal data-output command, the transmission-source address converter5 performs arrangement processing on the data output from thedata-transmission source 2 to the data buffer 4.

When the data-transmission destination 3 is a device to which data ispassively input, that is, when the data is input to thedata-transmission destination 3 from the data buffer 4 only if thedata-transmission destination 3 receives an external data-input command,the transmission-destination-address converter 6 performs arrangementprocessing on the data output from the data buffer 4 to thedata-transmission destination 3.

An embodiment of the present invention will be described below withreference to the drawings.

FIG. 2 is a block diagram showing a data transmitting-and-receivingsystem 100.

In the data transmitting-and-receiving system 100, a CPU 101 or a memory103 is selected as a data-transmission source which inputs data to astream buffer (memory device) 110, and one of the CPU 101, a CPU 102,the memory 103, and a memory 104 is selected for use as thedata-transmission destination to which data is output from the streambuffer 110.

For example, in FIG. 2, the CPU 101 is selected as the data-transmissionsource, and the memory 104 is selected as the data-transmissiondestination.

The stream buffer 110 includes an input port 111 that is connected tothe CPU 101; a data buffer 112 having a shift register 112 a and arandom access memory (RAM) 112 b for buffering the data input at theinput port 111 and an address controller 112 c that specifies read andwrite locations of the data buffered in the RAM 112 b as required; aninput-address converter 113 that can output the data input from theinput port 111 to the data buffer 112 (the data transferred to the databuffer 112) at a desired timing, as required; an output port 114 that isconnected to the memory 104; and an output-address converter 115 thatcan output the data output from the data buffer 112 to the memory 104(the data transferred to the memory 104) at a desired timing, asrequired.

The data output from the input port 111 is input to the shift register112 a or the RAM 112 b according to data-buffer access mode options A toF, described later (that is, the shift register 112 a or the RAM 112 bis selected).

Next, the configuration of each part in the stream buffer 110 will bedescribed.

FIG. 3 is a block diagram showing the internal configuration of theinput-address converter 113.

The input-address converter 113 includes a start-address register 121, acounter 122, an ALU 123, an access-address register 124, an end-addressregister 125, and a comparator 126.

The input-address converter 113 begins to operate when a registersetting command (described later) is input.

The start-address register 121 indicates a start address for datatransfer to the data buffer 112 and outputs the start address to the ALU123 when the register setting command is input thereto.

The counter 122 increments a count value for each access to theaccess-address register 124 and outputs the count value to the ALU 123.

The ALU 123 adds the count value in the counter 122 to the start addressoutput from the start-address register 121 and outputs the result to theaccess-address register 124.

When there is an output from the ALU 123, the access-address register124 outputs the value of the access-address register 124 to the inputport 111 and outputs the count value to the comparator 126.

The end-address register 125 stores the final address for the datatransfer to the data buffer 112.

The comparator 126 compares the value in the access-address register 124and the value in the end-address register 125 and, when they are equal,outputs a transfer-complete interrupt signal indicating completion ofthe data transfer.

FIG. 4 is a block diagram showing the internal configuration of theoutput-address converter 115.

The output-address converter 115 includes a start-address register 131,a counter 132, an ALU 133, an access-address register 134, anend-address register 135, and a comparator 136.

The output-address converter 115 begins operating when a registersetting command is input.

The start-address register 131 indicates a start address for datatransfer to the data-transmission destination (the memory 104 in thisembodiment) connected to the output side of the data buffer 112, andwhen the register setting command is input, it outputs the start addressto the ALU 133.

The counter 132 increments a count value for each access to theaccess-address register 134 and outputs the count value to the ALU 133.

The ALU 133 adds the count value in the counter 132 to the start addressoutput from the start-address register 131 and outputs the result to theaccess-address register 134.

When there is an output from the ALU 133, the access-address register134 outputs the value in the access-address register 134 to the outputport 114 and outputs the count value to the comparator 136.

The end-address register 135 stores the final address for the datatransfer to the memory 104.

The comparator 136 compares the value in the access-address register 134and the value in the end-address register 135, and when they are thesame, it outputs a transfer-complete interrupt signal.

FIG. 5 is a block diagram showing the internal configuration of theshift register 112 a.

The shift register 112 a includes n+1 buffers (where n is an integerequal to 1 or more), that is, buffer 0, buffer 1, . . . , buffer n-1,and buffer n.

Write addresses in the shift register 112 a start at buffer n andsequentially proceed through buffer n-1, buffer n-2, buffer n-3 . . . .Read addresses start at buffer 0 and sequentially proceed through buffer1, buffer 2, buffer 3, . . . .

FIG. 6 is a block diagram showing the configuration of the RAM 112 b andthe address controller 112 c.

The shift register 112 a is not shown in FIG. 6.

The RAM 112 b is formed of n+1 rows of buffers (where n is an integerequal to 1 or more) provided with a plurality of memory cells, that is,buffer 0, buffer 1, . . . , buffer n-1, and buffer n.

The address controller 112 c includes a write pointer (hereinafterreferred to as “WP”) generator 141 for generating a write pointer thatindicates the address (for write access) when writing data into the RAM112 b, a read pointer (hereinafter referred to as “RP”) generator forgenerating a read pointer that indicates the address (for read access)when reading data from the RAM 112 b, a write port 143, and a read port144.

The WP generated by the WP generator 141 is output to the RAM 112 b viathe write port 143. Likewise, the RP generated by the RP generator 142is output to the RAM 112 b via the read port 144.

Next, example configurations of the data transmitting-and-receivingsystem 100 will be described.

FIG. 7 is a table showing six example configurations of the datatransmitting-and-receiving system 100.

In FIG. 7, columns labeled “input side,” “output side,” “input-addressconverter,” “output-address converter,” “transfer mode,” and“data-buffer access mode” are arranged horizontally. Data items arrangedhorizontally are associated with each other and constitute informationfor each configuration.

The data-transmission source connected to the input side of the streambuffer 110 is shown in the “input side” column. In configurations 1, 3,and 4, the CPU 101 is selected as the data-transmission source, and inconfigurations 2, 5, and 6, the memory 103 is selected as thedata-transmission source.

The data-transmission destination connected to the output side of thestream buffer 110 is shown in the “output side” column. Inconfigurations 1 and 5, the memory 104 is selected as thedata-transmission destination, in configurations 2 and 3, the CPU 102 isselected as the data-transmission destination, in configuration 4, theCPU 101 is selected as the data-transmission destination, and inconfiguration 6, the memory 103 is selected as the data-transmissiondestination.

In configuration 4, the CPU 101 serves as both the data-transmissionsource and the data-transmission destination. Similarly, inconfiguration 6, the memory 103 serves as both the data-transmissionsource and the data-transmission destination.

In configurations 1 to 6, the selected CPU and memory are used incombination with the stream buffer 110.

The “input-address converter” column shows whether or not it isnecessary to use the input-address converter 113. (The circle indicatesYES and the cross indicates NO.)

When an active unit that initiates its own data transfer, such as theCPU 101, is connected to the input side of the stream buffer 110, theCPU 101 itself carries out data input to the stream buffer 110. Thus, inconfigurations 1, 3, and 4, since data transfer can be carried out at adesired timing without using the input-address converter 113, theinput-address converter 113 is not necessary.

On the other hand, when a passive unit such as the memory 103 isconnected to the input side of the stream buffer 110, in other words, inconfigurations 2, 5, and 6, the input-address converter 113 must be usedfor inputting data to the stream buffer 110 at a desired timing.

The “output-address converter” column indicates whether or not theoutput-address converter 115 needs to be used.

When an active unit that initiates its own data transfer, such as theCPU 102, is connected to the output side of the stream buffer 110, theCPU 102 itself performs data output from the stream buffer 110.Therefore, in configurations 2, 3, and 4, since data transfer can becarried out at a desired timing without using the output-addressconverter 115, the output address converter 115 is not necessary.

On the other hand, when a passive unit, such as the memory 103 or thememory 104, is connected to the output side of the stream buffer 110, inother words, in configurations 1, 5, and 6, the output-address converter115 must be used for outputting data from the stream buffer 110 at adesired timing.

The “transfer mode” column indicates whether or not a transfer mode canbe used. In configurations where a CPU is not used on at least one ofthe input side and the output side, the transfer mode indicates thatarrangement processing is performed on the data transferred from thedata-transmission source to the data buffer 112 or that arrangementprocessing is performed on the data transferred from the data buffer 112to the data-transmission destination. In this mode, the data istransferred a desired distance (spacing). The transfer mode can be usedin configurations 1, 2, 5, and 6. The transfer mode will be described indetail later.

The “data-buffer access mode” column specifies how the data is writtento the data buffer 112 or how the data is read out from the data buffer112. There are five options, options A to E, for the access mode.

The options A to E will be described next.

Option A

In option A, the shift register 112 a is selected as the storagelocation of the data.

When writing data to the shift register 112 a, the data is first writtenfrom the input port 111 into buffer n, and sequentially written tobuffer n-1, buffer n-2, . . . . When reading out the data, the data isread-out to the output port 114 beginning with buffer 0, and thensequentially read out from buffer 1, buffer 2, buffer 3, . . . . Inother words, in option A, the shift register 112 a (data buffer 112) isused as a first-in first-out (FIFO) buffer.

In option A, using the FIFO configuration allows seamless operation,regardless of the buffer capacity. Also, since it is possible to performcontrol of the data buffer 112 without using software, the versatilityis improved and the load on the CPU, which would normally increase whenexecuting software, is reduced.

In option A, the CPUs 101 and 102 and the memories 103 and 104 connectedto the stream buffer 110 can be selected independently. Therefore,option A can be selected in configurations 1 to 6.

Option B

In option B, the RAM 112 b is selected as the storage location of thedata.

In option B, the RAM 112 b is used as a FIFO buffer, like option A. Inoption B, specifying the WP and RP indicates the write address and theread address in the RAM 112 b, respectively. Because it is necessary tospecify the WP and RP, at least one of the CPU 101 and the CPU 102 mustbe connected to the stream buffer 110. Therefore, option B can beselected in configurations 1 to 4.

Next, the data writing and reading operations of the RAM 112 b in optionB will be described.

FIG. 8 is an outlined diagram showing an example of the writing andreading operations of the RAM 112 b in option B.

In order to make the following description more clear, the address wheredata is to be written and the address from which data is to be read areshown by arrows.

First, the WP and RP both point to buffer 0. This is the initial state.

Next, the WP points to buffer 1 (step S1). Thus, data is written intobuffer 1. At this time, since the RP points to buffer 0, data in buffer0 is read out. Next, the WP points to buffer 2 (step S2). Thus data iswritten into buffer 2. Next, the RP points to buffer 1 (step S3). Thus,data in buffer 1 is read out. Next, the RP points to buffer 0 (step S4).Thus, the data in buffer 0 is read out again. Next, the RP points tobuffer 1 (step S5). Thus, the data in buffer 1 is read out again.

In option B, the RAM 112 b is used as a FIFO buffer, similarly to optionA. Also, by “rewinding” the RP (the operations in steps S3 and S4), thesame data can be repeatedly extracted.

Option C

In option C, the RAM 112 b is selected as the storage location of thedata.

In option C, the data-transmission source connected to the input port111 directly specifies an address in the RAM 112 b. The readout of datais performed by specifying the RP. Because the address in the RAM 112 bmust be directly specified when writing, the CPU 101 must be connectedto the input port 111. Therefore, option B can be selected inconfigurations 1, 3, and 4.

In option C, data can be re-used and so the stream buffer 110 can beused like a memory.

Option D

In option D, the RAM 112 b is selected as the storage location of thedata.

In option D, the data-transmission destination connected to the outputport 114 directly specifies an address in the RAM 112 b. Data writing isperformed by specifying the WP. Because the address in the RAM 112 bmust be directly specified when reading, the CPU 101 or the CPU 102 mustbe connected to the output port 114. Therefore, option D can be selectedin configurations 2, 3, and 4.

In option D, data can be re-used and so the stream buffer 110 can beused like a memory.

Option E

In option E, the RAM 112 b is selected as the storage location of thedata.

In option E, the RAM 112 b is used as a first-in last-out (FILO) buffer.In option E, the RP indicates the address written to by using the WPimmediately before. Because the WP and RP must be specified, at leastone of the CPU 101 and the CPU 102 must be connected to the streambuffer 110. Therefore, option E can be selected in configurations 1 to4.

Next, the writing and reading operations of the RAM 112 b in option Ewill be described.

FIG. 9 is an outlined diagram showing an example of the writing andreading operations of the RAM 112 b in option E.

First, the WP and RP point to buffer 0. This is the initial state. Next,the WP points to buffer 1 (step S11). Thus, data is written into buffer1. At this time, because the RP points to buffer 0, the data in buffer 0is read out. Next, the WP points to buffer 2 and the RP points to buffer1 (step S12). Thus, data is written into buffer 2 and the data in buffer1 is read out. Next, the WP points to buffer 1 and the RP points tobuffer 0 (step S13). Thus, data is written into buffer 1 and the data inbuffer 0 is read out. Next, the WP points to buffer 0 (step S13). Thus,data is written into buffer 0.

In option E, since the RAM 112 b is used as a FILO buffer, it can beused as a stack memory, within the capacity of the RAM 112 b.

Next, Configurations 1 to 6 will be described in detail.

Configuration 1

FIG. 10 is a block diagram showing a data transmitting-and-receivingsystem of Configuration 1.

As shown in FIG. 10, a data transmitting-and-receiving system 100 aincludes the stream buffer 110, the CPU 101 provided at the input sideof the stream buffer 110, and the memory 104 provided at the output sideof the stream buffer 110. An ALU 130 is provided between the output port114 and the memory 104.

In this configuration, a case where option A is selected for the databuffer 112 will be described as a representative example.

For the sake of ease of comprehension of each figure from FIG. 10onwards, the components in the stream buffer 110 which are not selectedaccording to the options described above (in Configuration 1, theinput-address converter 113, the RAM 112 b, and the address controller112 c) will be omitted.

The CPU 101 outputs store commands, register setting commands, and so onand includes a command controller 117 to which various signals areinput, such as a busy signal and a transfer-complete interrupt signal,and a data cache 118 for caching data having a high level ofreusability.

The CPU 101 caches data having a high level of reusability in the datacache 118 and stores it in the memory 104 via the ALU 130. Also, the CPU101 outputs data having a low level of reusability to the shift register112 a via the input port 111 based on a store command and others.

The data buffered in the shift register 112 a is sequentially output tothe output port 114. When data read-out from the shift register 112 adoes not keep up with the data input based on the store command and allbuffers in the shift register 112 a become filled up with data, theshift register 112 a outputs a busy signal to the command controller 117in the CPU 101.

The output port 114 receives from the output-address converter 115 anaddress to be accessed in the memory 104 for transferring the data.

Here, the output-address converter 115 has three transfer modes, whichare described below, when transferring data to the memory 104.

First Transfer Mode

FIG. 11 is an outlined diagram showing a first transfer mode.

In the first transfer mode, m (where 1≦m≦n+1) data items areconsecutively transferred from a desired buffer in the shift register112 a (a desired start address in the RAM 112 b) to the memory 104. FIG.11 shows the memory 104 to which n+1 data items of data length X aretransferred according to the first transfer mode. Hereinafter, the firsttransfer mode is called a “consecutive access mode.”

The consecutive access mode is used in standard array access, forexample, when carrying out image processing in the horizontal directionin a two-dimensional arrangement of image data.

FIG. 12 is an outlined diagram showing an example in which theconsecutive access mode is used.

For example, when the address length (address 0 to address MAX) in thememory 104 and the address length of a full image that can be displayedin an image display region A of an image display device are set to bethe same, if predetermined data is to be displayed in region A1 (ashaded region in FIG. 12) inside the image display region A, theoutput-address converter 115 consecutively outputs data 0, data 1, data2, . . . , and data n from the output port 114 so that data 0, data 1,data 2, . . . , and data n are stored at addresses in the memory 104corresponding to the region A1. By doing so, the data transferred fromthe memory 104 to the image display device (not shown) is consecutivelydisplayed in the horizontal direction, as shown in FIG. 12.

Second Transfer Mode

FIG. 13 is an outlined diagram showing a second transfer mode.

In the second transfer mode, when transferring m data items to thememory 104, the computational function of the ALU 133 in theoutput-address converter 115 is modified to adjust the timing at whichvalues are output from the access-address register 134, so that, from adesired start address in the memory 104, a fixed distance from data itemto data item is maintained. FIG. 13 shows the memory 104 into which n+1data items of data length Y are to be transferred according to thesecond transfer mode. Hereinafter, the second transfer mode is referredto as the “distance access mode.” The distance access mode is used when,for example, two dimensional image data is consecutively displayed inthe vertical direction on an image display device.

FIG. 14 is an outlined diagram showing an example in which the distanceaccess mode is used.

When the address length of the memory 104 (address 0 to address MAX) andthe address length of the largest image data displayed in an imagedisplay region A on the image display device are set to be the same, ifpredetermined data is to be displayed in a region A2 (a shaded region inFIG. 14) in the image display region A, the output-address converter 115outputs data 0, data 1, data 2, . . . , and data n from the output port114 so that the data is stored in the memory 104 in such a manner thatthe region between data 0 and data 1 in the region A2 corresponds to thedistance shown in FIG. 13. By doing so, the data transferred from thememory 104 to the image display device (not shown) is displayed so as tobe separated by a predetermined distance, and as a result, the data isconsecutively displayed in the vertical direction.

Third Transfer Mode

FIG. 15 is an outlined diagram showing a third transfer mode.

In the third transfer mode, when n+1 data items are transferred to thememory 104, the calculation function of the ALU 133 in the outputaddress converter 115 is modified to adjust the timing at which valuesare output from the access address register 134 so that, from a desiredstart address in the memory, a plurality of blocks formed of m (where mis an integer less than or equal to n+1) data items of data length W,each maintaining a fixed distance (distance 0) from data item to dataitem, maintain a fixed distance (distance 1) from block to block. FIG.15 shows the memory 104 into which n+1 data items of data length Z aretransferred according to the third transfer mode. Hereinafter, the thirdtransfer mode is referred to as a “multi-distance access mode.” Themulti-distance access mode is used when, for example, two-dimensionalimage data is to be displayed in a predetermined rectangular region onan image display device.

FIG. 16 is an outlined diagram showing an example in which themulti-distance access mode is used.

For example, when the address length (address 0 to address MAX) in thememory 104 and the address length of the largest image data displayed inan image display region A on an image display device are set to beequal, if predetermined data is to be displayed in region A3 (a shadedregion in FIG. 16) in the image display region A, the output-addressconverter 115 outputs data 0, data 1, data 2, . . . , and data n fromthe output port 114 so that the data is stored in the memory 104 in sucha manner that the distance between data 0 and data 1 in region A3corresponds to distance 0 shown in FIG. 15, and the distance between theend of each row in region A3 and the beginning of the next rowcorresponds to distance 1. By doing so, the data transferred from thememory 104 to the image display device (not shown) is displayed so as tobe separated by a predetermined distance, and as a result, the data isconsecutively displayed in the vertical direction.

By suitably applying these three transfer modes depending on thesituation, it is possible to store data at desired addresses in thememory 104.

Next, the operation of the data transmitting-and-receiving system 100 awill be described.

First, before executing software for using the stream buffer 110, thestream buffer 110 is initialized. More concretely, the start-addressregister 131 and the end-address register 135 in the output-addressconverter 115 are configured based on a register setting command fromthe CPU 101 (which may be a dedicated command, or it may be implementedas a special address store command).

Next, the software for actually using the stream buffer 110 is started.The software outputs generated data from the CPU 101 as store data.(This embodiment shows an example which is implemented by store commandshaving a fixed address indicating the stream buffer, without using aspecial command in a store operation in the stream buffer.)

The store command input to the stream buffer 110 is stored as requiredin the data buffer 112 via the input port 111.

Next, the output-address converter 115 copies the contents of thestart-address register 131, for outputting the initial data, to theaccess-address register 134 via the ALU 133. Then, the access-addressregister 134 outputs the value in the access-address register 134 to theoutput port 114 and increments the value in the counter 132.

The output port 114 accesses the memory 104 when the access-addressregister 134 outputs the value (that is, at the timing of the outputvalue from the access address register 134).

With this data transmitting-and-receiving system 100 a of Configuration1, it is possible to transfer data having a low level of reusability tothe memory 104 without going via the data cache 118.

Configuration 2

Next a data transmitting-and-receiving system of Configuration 2 will bedescribed.

FIG. 17 is a block diagram showing the transmitting-and-receiving systemin Configuration 2.

In the following, a data transmitting-and-receiving system 100 b ofConfiguration 2 will be described by focusing on the differences fromthe data transmitting-and-receiving system 100 a described above, and adescription of similarities will be omitted.

The data transmitting-and-receiving system 100 b of Configuration 2includes the stream buffer 110, the memory 103 provided at the inputside of the stream buffer 110, and the CPU 102 provided at the outputside of the stream buffer 110.

The stream buffer 110 in Configuration 2 reads out data from the memory103 asynchronously with respect to the CPU 102 via the input port 111,and the CPU 102 extracts data from the stream buffer 110 based on a loadcommand (or an operation corresponding thereto).

The input-address converter 113 determines whether or not the databuffer 112 is full and controls the issuing of requests to the memory.

Therefore, the parts of the stream buffer 110 used in Configuration 2are the input port 111, the data buffer 112, the input-address converter113, and the output port 114.

The transfer modes are used in Configuration 2 when data is transferredfrom the memory 103 to the data buffer 112.

The transfer modes used in Configuration 2 are described below, but thedescription focuses on the differences from the transfer mode used inConfiguration 1 described above, and a description of any similaritiesis omitted.

Consecutive Access Mode

In the consecutive access mode in Configuration 2, m data items areconsecutively transferred to the shift register 112 a starting at apredetermined start address in the memory 103.

Distance Access Mode

In the distance access mode in Configuration 2, when m data items aretransferred to the shift register 112 a, the computational function ofthe ALU 123 in the input-address converter 113 is modified to adjust thetiming at which values are output from the access-address register 124,so that a fixed distance is maintained from data item to data item froma desired buffer in the shift register 112 a.

Multi-Distance Access Mode

In the multi-distance access mode in Configuration 2, when n+1 dataitems are transferred to the shift register 112 a, the computationalfunction of the ALU 123 in the input-address converter 113 is modifiedto regulate the timing at which values are output from theaccess-address register 124 so that, from a predetermined start addressin the memory 104, a plurality of blocks formed of m data items (where mis an integer less than or equal to n+1), each maintaining a fixeddistance (distance 0) from data item to data item, maintain a fixeddistance (data length 0) from block to block.

Next, the operation of the data transmitting-and-receiving system 100 bof Configuration 2 will be described.

First, prior to executing software for actually using the stream buffer110, the stream buffer 110 is initialized. Concretely, the start-addressregister 121 and the end-address register 125 in the input-addressconverter 113 are configured based on register setting commands from theCPU 102 (these may be dedicated commands or they may be implemented asspecial address store commands).

Next, activation of data transfer with the stream buffer 110 isinstructed. More concretely, an activation instruction is sent to theaccess-address register 124 based on a register setting command from thecommand controller 107.

When the access-address register 124 receives the instruction to startdata transfer, the contents of the start-address register 121 are firstcopied to the access-address register 124 for the initial data input inthe input-address converter 113. Next, the access-address register 124outputs the value in the access address register 124 to the input port111.

The input port 111 accesses the shift register 112 a when the value isoutput from the access-address register 124 (that is, at the timing ofthe output value from the access-address register 124).

The access address register 124 increments the value in the accessaddress register 124 every time when each data item is output to theinput port 111.

The comparator 126 compares the value in the end-address register 125and the value in the access-address register 124, and when these valuesare equal, it outputs a transfer-complete interrupt signal to thecommand controller 107.

After issuing the data transfer instruction, the CPU 102 executes thesoftware for actually using the stream buffer 110 at a desired timing.The software reads out data from the stream buffer 110 as required. Thisembodiment shows an example implemented by a load command having a fixedaddress indicating the stream buffer 110, without using a specialcommand in the load operation from the stream buffer 110. In thisembodiment, it is assumed that, when there is not yet any data whenreading from the stream buffer 110 (that is, when the data buffer isempty), the stream buffer 110 does not return any data and causes theCPU 102 to wait.

In the data transmitting-and-receiving system 100 b of Configuration 2,the same advantages as those of the data transmitting-and-receivingsystem 100 a described above can be obtained. In other words, datahaving a low level of reusability, which is used by the CPU, can be readout from the memory without passing through a cache memory.

Configuration 3

Next, a data transmitting-and-receiving system of Configuration 3 willbe described.

FIG. 18 is a block diagram showing the transmitting-and-receiving systemof Configuration 3.

In the following, a data transmitting-and-receiving system 100 c ofConfiguration 3 will be described by focusing on the differences fromthe data transmitting- and receiving systems 100 a and 100 b describedabove, and a description of similarities will be omitted.

The data transmitting-and-receiving system 100 c of Configuration 3,which functions as a communication buffer between two different CPUs,includes the stream buffer 110, the CPU 101 provided at the input sideof the stream buffer 110, and the CPU 102 provided at the output side ofthe stream buffer 110.

When the CPUs 101 and 102 are connected to the input and output sides ofthe stream buffer 110, respectively, data inputting to the stream buffer110 is carried out by the CPU 101 itself, and data outputting from thestream buffer 110 is carried out by the CPU 102 itself. Therefore, inConfiguration 3, neither the input-address converter 113 noroutput-address converter 115 is used. As a result, the componentsconstituting the stream buffer 110 used in Configuration 3 are the inputport 111, the output port 114, and the data buffer 112.

In Configuration 3, because a desired address and data to be stored atthe address can be set in the CPU 101 and the CPU 102, it is notnecessary to change the transfer mode when transmitting data. Therefore,a transfer mode option does not need to be set in Configuration 3.

The data transmitting-and-receiving system 100 c in Configuration 3 canachieve the same advantages as the data transmitting-and-receivingsystems 100 a and 100 b described above.

Configuration 4

Next, a data transmitting-and-receiving system of Configuration 4 willbe described.

FIG. 19 is a block diagram showing the transmitting-and-receiving systemof Configuration 4.

In the following, a data transmitting-and-receiving system 100 d inConfiguration 4 will be described by focusing on the differences fromthe data transmitting-and-receiving system 100 c described above, and adescription of similarities will be omitted.

The data transmitting-and-receiving system 100 d in Configuration 4includes the stream buffer 110 and the CPU 101, which is connected tothe input and output sides of the stream buffer 110.

When the CPU 101 is connected to the input and output sides of thestream buffer 110, data inputting to the stream buffer 110 and dataoutputting from the stream buffer 110 are performed by the CPU 101itself. Therefore, in Configuration 4, neither the input-addressconverter 113 nor the output-address converter 115 is used. As a result,the components constituting the stream buffer 110 used in Configuration4 are the input port 111, the output port 114, and the data buffer 112.

In Configuration 4, like Configuration 3, because a desired address anddata to be stored at the address can be set in the CPU 101, a transfermode option does not need to be set.

The data transmitting-and-receiving system 100 d in Configuration 4 canachieve the same advantages as the data transmitting-and-receivingsystem 100 c described above.

In particular, the data transmitting-and-receiving system 100 d inConfiguration 4 can function as a stack memory which the CPU 101 uses,by adopting the functions of option D and option E for the stream buffer110. Furthermore, it can also function as a communication buffer betweendifferent processes in the same CPU 101.

Configuration 5

Next, a data transmitting-and-receiving system of Configuration 5 willbe described.

FIG. 20 is a block diagram showing the data transmitting-and-receivingsystem of Configuration 5.

In the following, a data transmitting-and-receiving system 100 e ofconfiguration 5 will be described by focusing on the differences fromthe data transmitting-and-receiving systems 100 a and 100 b describedabove, and a description of similarities will be omitted.

The data transmitting-and-receiving system 100 e of Configuration 5includes the stream buffer 110, the memory 103 provided at the inputside of the stream buffer 110, and the memory 104 provided at the outputside of the stream buffer 110.

When a passive unit, such as the memory 103, is connected to the inputside of the stream buffer 110, the input-address converter 113 in thestream buffer 110 performs timing control (address control of the databuffer 112) of the data to be stored in the data buffer 112 and requeststhe memory 103 to transfer data to input the data into the stream buffer110.

On the other hand, when a passive unit, such as the memory 104, isconnected to the output side of the stream buffer 110, theoutput-address converter 115 in the stream buffer 110 performs addresscontrol of the data buffer 112 and performs data transfer with thememory 104 to output the data from the stream buffer 110.

Initialization of the stream buffer 110 in this Configuration isperformed by providing a separate storage unit in the stream buffer 110and loading initial-setting commands from the storage unit. Also,register setting commands may be externally input and initializationcarried out based on those commands.

The data transmitting-and-receiving system 100 e of Configuration 5 canachieve the same advantages as the data transmitting-and-receivingsystems 100 a and 100 b described above.

Furthermore, in the data transmitting-and-receiving system 100 e, thestream buffer 110 can provide a direct memory access (DMA) function forperforming block transfer from a predetermined region in the memory toanother region, without passing through a CPU.

The data transfer mode employed by the output-address converter 115 maybe the same as the data transfer mode employed by the input-addressconverter 113, or it may be different.

Configuration 6

Next, a data transmitting-and-receiving system of Configuration 6 willbe described.

FIG. 21 is a block diagram showing the data transmitting-and-receivingsystem of Configuration 6.

In the following, a data transmitting-and-receiving system 100 f ofConfiguration 6 will be described by focusing on the differences fromthe data transmitting-and-receiving system 100 e described above, and adescription of similarities will be omitted.

The data transmitting-and-receiving system 100 f of Configuration 6includes the stream buffer 110 and the memory 103 provided at the inputand output sides of the stream buffer 110.

When the memory 103 is connected to the input and output sides of thestream buffer 110, data inputting to the stream buffer 110 and dataoutputting from the stream buffer 110 are performed by the input-addressconverter 113 and the output-address converter 115, respectively.

Therefore, the components constituting the stream buffer 110 used inConfiguration 6 are the input-address converter 113, the output-addressconverter 115, the input port 111, the output port 114, and the databuffer 112.

This data transmitting-and-receiving system 100 f of Configuration 6 canachieve the same advantages as the data transmitting-and-receivingsystem 100 e described above.

Furthermore, in the data transmitting-and-receiving system 100 f ofConfiguration 6, the stream buffer 110 can function as a transfer bufferbetween a plurality of memory hierarchies, for example, between alevel-1 cache and the main memory, between a level-1 cache and a level-2cache, and so on. Also, the stream buffer 110 can be used in datatransfer from the local memory of a certain CPU to the local memory ofanother CPU.

As described above, with the data transmitting-and-receiving systems 100a to 100 f (the stream buffer (memory device) 110) of the presentembodiment, data transmission and reception can be reliably performedwithout changing the hardware configuration of the stream buffer 110,regardless of whether the CPUs 101 and 102 and the memories 103 and 104are connected to the stream buffer 110. Accordingly, it is possible tofacilitate system development.

It is also possible to realize an efficient, dedicated data bus withoutwastefully using up the capacity of a cache memory (that is, withoutoccupying a part of the cache memory meaninglessly), even for data thatis not reusable.

When option A is selected, because the shift register 112 a is mainlycontrolled by the hardware of the stream buffer 110, it is possible tosimplify the configuration of the data transmitting-and-receiving systemwithout the data-transmission destination connected to the output sideof the stream buffer 110 performing any special software control.

Furthermore, by specifying the data transfer option, data can be storedat desired addresses in the memories 103 and 104.

In addition, by setting options A to E, desired data can be stored atdesired addresses in the memories 103 and 104.

Accordingly, after storing the data at those addresses in the memories103 and 104, it is possible to omit processing for rearrangement, whichis normally carried out at a later stage by separate software.

Although the memory device of the present invention has been describedbased on the embodiment shown in the drawings, the present invention isnot limited thereto; individual components may be replaced with othercomponents having the same functionality. Also, in the presentinvention, various other additional parts and processes may be included.

For example, by adopting a configuration in which an address controllerfor managing a memory separate from the data buffer 112, as well asaddresses for that memory, is provided in the stream buffer 110 andoverflow data from the data buffer 112 is temporarily saved in thatmemory, it is possible to realize a stack memory that is not limited tothe capacity of the data buffer 112.

Furthermore, in the present invention, two or more configurations(features) described in the embodiment above may be combined.

Although a description has been given of an example in which the CPUs101 and 102 and the memories 103 and 104 are connected to the input port111 and the output port 114, the invention is not limited thereto. Forexample, I/O devices may also be connected.

The address controller 112 c is provided in the data buffer 112 in theembodiment described above. However, the invention is not limited tothis arrangement; the address controller 112 c needs to be provided inthe stream buffer 110.

According to the present invention, regardless of the data-transmissionsource and the data-transmission destination connected to the memorydevice, it is possible to reliably carry out data transmission andreception without changing the hardware configuration of the memorydevice. Accordingly, it is possible to facilitate system development.

Using the transmission-source address converter and thetransmission-destination address converter to perform arrangementprocessing as required enables the elimination of separatesoftware-based rearrangement after this processing.

The foregoing is considered as illustrative only of the principles ofthe present invention. Further, since numerous modifications and changeswill readily occur to those skilled in the art, it is not desired tolimit the invention to the exact construction and applications shown anddescribed and accordingly, all suitable modifications and equivalentsmay be regarded as falling within the scope of the invention in theappended claims and their equivalents.

1. A memory device for use in transmission and reception of data,comprising: a data buffer for storing data output from adata-transmission source and for outputting the data to adata-transmission destination serving as an output destination of thedata; a transmission-source address converter for performing arrangementprocessing on the data output from the data-transmission source when thedata-transmission source is a device that passively outputs data; and atransmission-destination address converter for performing arrangementprocessing on the data to be input to the data-transmission destinationwhen the data-transmission destination is a device to which data ispassively input.
 2. The memory device according to claim 1, wherein thedata-transmission source is one of a CPU and a memory; and when thedata-transmission source is the memory, the transmission-source addressconverter performs the arrangement processing.
 3. The memory deviceaccording to claim 2, wherein the CPU also serves as thedata-transmission destination.
 4. The memory device according to claim2, wherein the memory also serves as the data-transmission destination.5. The memory device according to claim 1, wherein the data-transmissiondestination is one of a CPU and a memory; and when the data-transmissiondestination is the memory, the transmission-destination addressconverter performs the arrangement processing.
 6. The memory deviceaccording to claim 1, wherein the arrangement processing is processingfor consecutively transferring the data.
 7. The memory device accordingto claim 1, wherein the arrangement processing is processing fortransferring the data while maintaining a fixed spacing between dataitems of the data.
 8. The memory device according to claim 1, whereinthe arrangement processing is processing in which a plurality of datablocks maintaining a fixed spacing between data items of the data areformed, and each data block is transferred while maintaining a fixedspacing.
 9. The memory device according to claim 1, wherein thetransmission-source address converter and the transmission-destinationaddress converter perform different arrangement processing.
 10. Thememory device according to claim 1, wherein the data buffer isconfigured to perform first-in first-out control.
 11. The memory deviceaccording to claim 1, further comprising an address controller forperforming sequence control of the data buffer based on a write pointerindicating a write destination address of the data in the data buffer byinputting a write signal and a read pointer indicating a read sourceaddress of the data in the data buffer by inputting a read signal. 12.The memory device according to claim 11, further comprising: awrite-pointer generator for generating the write pointer; and aread-pointer generator for generating the read pointer.